The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2010

Filed:

Apr. 12, 2006
Applicants:

Jon M. Mcgary, Round Rock, TX (US);

Brian L. Brelsford, Austin, TX (US);

Timothy M. Lambert, Austin, TX (US);

Inventors:

Jon M. McGary, Round Rock, TX (US);

Brian L. Brelsford, Austin, TX (US);

Timothy M. Lambert, Austin, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method is disclosed for programming a field programmable gate array. The system involves the recognition of the next following bit sequence to be transmitted to the FPGA through a general purpose input output device. Once the bit sequence is identified, the data line is only changed at the GPIO in those instances in which the next succeeding data bit in the bit sequences is different from the preceding data bit. In those situations in which the next following bit sequence is not different, the clock line is triggered without the necessity of testing, and changing the logic level of the data line.


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