The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2010
Filed:
May. 12, 2006
Anna Wing Wah Wong, Santa Clara, CA (US);
Jennifer Wong, Fremont, CA (US);
Bernard J. New, Carmel Valley, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
John M. Thendean, Berkeley, CA (US);
James M. Simkins, Park City, UT (US);
Vasisht Mantra Vadi, San Jose, CA (US);
David P. Schultz, San Jose, CA (US);
Anna Wing Wah Wong, Santa Clara, CA (US);
Jennifer Wong, Fremont, CA (US);
Bernard J. New, Carmel Valley, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
John M. Thendean, Berkeley, CA (US);
James M. Simkins, Park City, UT (US);
Vasisht Mantra Vadi, San Jose, CA (US);
David P. Schultz, San Jose, CA (US);
XILINX, Inc., San Jose, CA (US);
Abstract
An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.