Duty cycle correction methods and circuits

Abstract

Duty cycle correction (DCC) methods and circuits are provided for improving the quality of clock signals and reducing or eliminating duty cycle distortion. The performance of known duty cycle correction circuits, such as cross-coupled inverter or transmission gate DCC circuits, may be improved by coupling two or more DCC circuits in series to form a multi-stage DCC circuit. In multi-stage DCC circuits, the performance and sizing requirements imposed on the individual circuit stages are reduced as compared to single-stage DCC circuit implementations. Good duty cycle correction performance over a wide range of input signal duty cycles may therefore be ensured regardless of the performance of individual stages. Clocked-CMOS DCC circuits are also presented, the circuits operative to produce duty cycle corrected output signals while consuming minimal current and power. The clocked-CMOS DCC circuits include as few as four transistors, and are operative over wide ranges of input signal duty cycles.