The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2010
Filed:
Dec. 09, 2008
Chua-chin Wang, Kaohsiung, TW;
Tzung-je Lee, Kaohsiung, TW;
Yi-cheng Liu, Kaohsiung, TW;
Kuo-chan Huang, Sinshih Township, Tainan County, TW;
Chua-Chin Wang, Kaohsiung, TW;
Tzung-Je Lee, Kaohsiung, TW;
Yi-Cheng Liu, Kaohsiung, TW;
Kuo-Chan Huang, Sinshih Township, Tainan County, TW;
Himax Technologies Limited, Sinshih Township, Tainan County, TW;
National Sun Yat-Sen University, Kaohsiung, TW;
Abstract
An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.