The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2010

Filed:

Aug. 11, 2009
Applicants:

Wenfeng Zhang, San Jose, CA (US);

Qi Zhang, Chandler, AZ (US);

Jian Tan, Fremont, CA (US);

Inventors:

Wenfeng Zhang, San Jose, CA (US);

Qi Zhang, Chandler, AZ (US);

Jian Tan, Fremont, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for signal level shifting in an IC can include a first inverter having a first pull-up device and a pull-down device, wherein the first inverter is operable to receive an input signal having a voltage potential at a logic high that does not disable the first pull-up device. The system can include a second inverter coupled in series to an output of the first inverter, and a control module coupled to the output of the first inverter and an output of the second inverter. Prior to the input signal transitioning to the logic high, the control module is operable to decouple the input signal from the first pull-up device, disable the first pull-up device, and close a feedback loop that latches an output state of the second inverter.


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