The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2010

Filed:

Dec. 19, 2005
Applicants:

Youri Ponomarev, Leuven, BE;

Josine Loo, Leuven, BE;

Inventors:

Youri Ponomarev, Leuven, BE;

Josine Loo, Leuven, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a semiconductor device () having a semiconductor body (), comprising a field effect transistor, a first gate dielectric (A) being formed on a first surface at the location of the channel region () and on it a first gate electrode (), a sunken ion implantation () being executed from the first side of the semiconductor body () through and on both sides of the first gate electrode (), which implantation results in a change of property of the silicon below the first gate electrode () compared to the silicon on both sides of the gate electrode) in a section of the channel region () remote from the first gate dielectric (A), and on the second surface of the semiconductor body () a cavity () being provided therein by means of selective etching while use is made of the change of property of the silicon. A second gate (B,) is deposited in the cavity thus formed. Before the ion implantation (), a mask (M) is formed on both sides of the gate electrode () and at a distance thereof, whereby after the ion implantation () at the location of the mask (M) also a change in property of the silicon is obtained. In this way the device () can be easily provided with lateral insulation regions. Also the end regions of the gate electrodes () can in this way be surrounded by insulation regions.


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