The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2010

Filed:

Feb. 10, 2006
Applicants:

Paul D. Brabant, Phoenix, AZ (US);

Joe P. Italiano, Phoenix, AZ (US);

Jianqing Wen, Singapore, SG;

Inventors:

Paul D. Brabant, Phoenix, AZ (US);

Joe P. Italiano, Phoenix, AZ (US);

Jianqing Wen, Singapore, SG;

Assignee:

ASM America, Inc., Phoenix, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.


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