The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2010
Filed:
Nov. 16, 2007
Shen Wang, Yokohama, JP;
Tetsuaki Utsumi, Kawasaki, JP;
Mizue Sekine, Tokyo, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor layout design apparatus has an inter-block connection information extracting part, a cell initial placement part and an evaluation value. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The cell initial placement part configured to initially place the standard cells and the macrocells in an placement region to generate an initial floor plan. The evaluation value calculating part configured to calculate an evaluation value of the floor plan based on distances between a plurality of blocks including the standard cells and the macrocells initially placed by the cell initial placement part and the extracted number of the wiring connections between a plurality of blocks.