The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2010
Filed:
Mar. 24, 2008
William A. Binder, Morrisville, NC (US);
Christopher J. Gonzalez, Shelburne, VT (US);
Paul D. Kartschoke, Williston, VT (US);
Sherwin C. Murphy, Jr., Cary, NC (US);
William A. Binder, Morrisville, NC (US);
Christopher J. Gonzalez, Shelburne, VT (US);
Paul D. Kartschoke, Williston, VT (US);
Sherwin C. Murphy, Jr., Cary, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a hierarchical netlist of the design, wherein the design includes a plurality of macros. The method also includes determining the timing slack of each path of the design. For each pin of each one of the plurality of macros, the method includes: determining the worst timing path; determining the slack value of the worst timing path; determining the subset of macros of the plurality of macros associated with the worst timing path; determining an apportionment parameter for each one of the subset of macros; determining a distribution of the slack amongst the subset of macros based upon the respective apportionment parameters; and adjusting timing assertions for each one of the subset of macros based upon the distribution of the slack.