Apparatus with variable pipeline stages via unification processing and cancellation

Abstract

To satisfy a required processing speed and achieve the maximum power-saving effect in a microprocessor. A control value is calculated by performing proportional and integral processing on a deviation of a target instruction execution number from a measured instruction execution number. Unification processing or unification cancellation processing is performed in accordance with the control value. The unification processing stops supply of clocks to selected pipeline registers and controls the pipeline such that a signal passes through the pipeline registers so as to reduce the number of stages of the pipeline. The unification cancellation processing resumes the supply of clocks to the selected pipeline registers and controls the pipeline such that the pipeline registers latch the signal in synchronism with the clocks so as to increase the number of stages of the pipeline. The frequency of clocks supplied to the pipeline registers is changed in accordance with the changed number of stages.