System and method for hardware payload header suppression, expansion, and verification in a wireless network

Abstract

The present invention provides methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header. The data packet, including the suppressed packet header and suppression index are then transmitted. Once received, a payload header suppress circuit on the receiver end examines the payload header suppression index to determine if the payload header has been suppressed. For each suppressed payload header, each bit in the payload header is compared to a payload header suppression mask to determine if the bit has been suppressed. Next, for each suppressed bit, a byte string is retrieved from a payload header suppression rule and inserted into the suppressed payload header.