The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2010
Filed:
May. 06, 2009
Shoji Kawahito, Hamamatsu, JP;
Zheng Liu, Hamamatsu, JP;
Yasuhide Shimizu, Isahaya, JP;
Kuniyuki Tani, Ogaki, JP;
Akira Kurauchi, Kawasaki, JP;
Koji Sushihara, Ikoma, JP;
Koichiro Mashiko, Takarazuka, JP;
Shoji Kawahito, Hamamatsu, JP;
Zheng Liu, Hamamatsu, JP;
Yasuhide Shimizu, Isahaya, JP;
Kuniyuki Tani, Ogaki, JP;
Akira Kurauchi, Kawasaki, JP;
Koji Sushihara, Ikoma, JP;
Koichiro Mashiko, Takarazuka, JP;
Semiconductor Technology Academic Research Center, Kanagawa, JP;
Abstract
A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.