The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2010

Filed:

May. 30, 2008
Applicants:

Phat Truong, Houston, TX (US);

Jon Nguyen, Richmond, VA (US);

Inventors:

Phat Truong, Houston, TX (US);

Jon Nguyen, Richmond, VA (US);

Assignee:

Nanya Technology Corp., Kueishan, Tao-Yuan Hsien, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced.


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Truong, Phat. (2010). Method to reduce variation in cmos delay (U.S. Patent No. 7834683). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7834683

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