The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2010
Filed:
Jun. 11, 2007
Francky Catthoor, Temse, BE;
Peng Yang, Leuven, BE;
Chun Wong, Leuven, BE;
Paul Marchal, Blanden, DE;
Aggeliki Prayati, Athens, GR;
Nathalie Cossement, Rekkem, BE;
Rudy Lauwereins, Winksele, BE;
Francky Catthoor, Temse, BE;
Peng Yang, Leuven, BE;
Chun Wong, Leuven, BE;
Paul Marchal, Blanden, DE;
Aggeliki Prayati, Athens, GR;
Nathalie Cossement, Rekkem, BE;
Rudy Lauwereins, Winksele, BE;
Interuniversitair Microelektronica Centrum (IMEC), Leuven, BE;
Katholieke Universiteit Leuven, Leuven, BE;
University of Patras, Patras, GR;
Abstract
A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a 'grey-box' description of the essentially digital system.