The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2010
Filed:
Nov. 16, 2007
Shen Wang, Yokohama, JP;
Tetsuaki Utsumi, Kawasaki, JP;
Mizue Sekine, Tokyo, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor layout design apparatus has an inter-block connection information extracting part, a block global placement part and a cell placement setting part. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The block global placement part configured to roughly place the plurality of blocks in a placement region on a semiconductor substrate. The cell placement setting part configured to set placement positions of the macrocells in the block based on a positioning relationship with the other block and the number of the wiring connections with the other block with respect to each of the plurality of blocks roughly placed by the block global placement part.