The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2010
Filed:
Dec. 13, 2002
George Wayne Nation, Eyota, MN (US);
Gary Scott Delp, Rochester, MN (US);
William D. Scharf, San Jose, CA (US);
Narayanan Raman, Milpitas, CA (US);
John N. Fryar, Iii, Apex, NC (US);
Majid Bemanian, Pleasanton, CA (US);
George Wayne Nation, Eyota, MN (US);
Gary Scott Delp, Rochester, MN (US);
William D. Scharf, San Jose, CA (US);
Narayanan Raman, Milpitas, CA (US);
John N. Fryar, III, Apex, NC (US);
Majid Bemanian, Pleasanton, CA (US);
LSI Corporation, Milpitas, CA (US);
Abstract
A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.