Synchronous detecting circuit

Abstract

In a synchronous detection circuit, an interpolation circuit regulates an interpolation calculation coefficient based on phase shift information when carrying out interpolation calculation processing over a digitally converted received signal. A sampling circuit samples interpolation data using a recovered clock as a reference and two clocks having phases which are advanced and delayed with respect to the recovered clock. A phase shift detecting circuit monitors a phase shift using three sampling data output from the sampling circuit and outputting phase shift information to the interpolation circuit when detecting a predetermined phase shift. A demodulating circuit performs demodulation processing using the data subjected to the sampling with the recovered clock output from the sampling circuit. Where a synchronous shift is detected, the interpolation circuit performs regulation to match a timing having a maximum signal-to-noise ratio and the recovered clock based on the amount of the phase shift.