The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2010
Filed:
Apr. 21, 2008
A. Peter Cosmin, San Jose, CA (US);
Sorin S. Georgescu, San Jose, CA (US);
George Smarandoiu, San Jose, CA (US);
Adrian M. Tache, Buccresti, RO;
A. Peter Cosmin, San Jose, CA (US);
Sorin S. Georgescu, San Jose, CA (US);
George Smarandoiu, San Jose, CA (US);
Adrian M. Tache, Buccresti, RO;
Semiconductor Components Industries, L.L.C., Phoenix, AZ (US);
Abstract
A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.