The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2010

Filed:

Jul. 27, 2005
Applicants:

Chul-woo Kim, Seoul, KR;

Jin-han Kim, Suwon-si, KR;

Seok-ryung Yoon, Seoul, KR;

Young-ho Kwak, Seoul, KR;

Seok-soo Yoon, Changwon-si, KR;

Inventors:

Chul-Woo Kim, Seoul, KR;

Jin-Han Kim, Suwon-si, KR;

Seok-Ryung Yoon, Seoul, KR;

Young-Ho Kwak, Seoul, KR;

Seok-Soo Yoon, Changwon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.


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