The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2010

Filed:

Dec. 12, 2007
Applicants:

Daisuke Uchimoto, Kyoto, JP;

Manabu Oyama, Kyoto, JP;

Inventors:

Daisuke Uchimoto, Kyoto, JP;

Manabu Oyama, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A minimum pulse signal generating circuit generates a minimum pulse signal having a predetermined minimum duty ratio, synchronously with a PWM signal. When the duty ratio of the PWM signal is smaller than the minimum duty ratio, a corrected pulse signal generating circuit fixes the logical level of the PWM signal to the level that turns off a switching transistor. A driver circuit drives the switching transistor according to a corrected PWM signal output from the corrected pulse signal generating circuit. In a case in which the level of the PWM signal is fixed by means of the corrected pulse signal generating circuit, a stop signal generating circuit generates a stop signal at a predetermined first level. When the stop signal is at the predetermined first level, at least an oscillator used for pulse modulation is stopped.


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