The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2010

Filed:

Jun. 30, 2007
Applicants:

Calvin K. LI, Fremont, CA (US);

Yung-tin Chen, Santa Clara, CA (US);

En-hsing Chen, Fremont, CA (US);

Paul Wai Kie Poon, Fremont, CA (US);

Inventors:

Calvin K. Li, Fremont, CA (US);

Yung-Tin Chen, Santa Clara, CA (US);

En-Hsing Chen, Fremont, CA (US);

Paul Wai Kie Poon, Fremont, CA (US);

Assignee:

SanDisk Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
Abstract

Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.


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