The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2010
Filed:
Mar. 10, 2005
Kentaro Nomoto, Hamakita, JP;
Yuki Igawa, Hamamatsu, JP;
Hiroshi Saitoh, Iwata-gun, JP;
Takashi Sato, Hamamatsu, JP;
Toshio Ohashi, Hamakita, JP;
Yoshihiro Ohkura, Iwata-gun, JP;
Kentaro Nomoto, Hamakita, JP;
Yuki Igawa, Hamamatsu, JP;
Hiroshi Saitoh, Iwata-gun, JP;
Takashi Sato, Hamamatsu, JP;
Toshio Ohashi, Hamakita, JP;
Yoshihiro Ohkura, Iwata-gun, JP;
Yamaha Corporation, Shizuoka-ken, JP;
Abstract
A semiconductor device, encapsulated in a wafer level chip size package (WLCSP), includes a plurality of pad electrodes formed on the surface of a semiconductor chip, wherein a first insulating layer is formed on the surface of the semiconductor chip except the pad electrodes; a plurality of connection electrodes and at least one heat-dissipation electrode are formed on the surface of the first insulating layer; the pad electrodes and the connection electrodes are mutually connected via a first wiring portion; the heat-dissipation electrode is connected with a second wiring portion; and a second insulating layer is formed to enclose the electrodes and wiring portions, wherein the second wiring portion is arranged in proximity to a heating portion of the semiconductor chip and is formed on the surface of the first insulating layer except the prescribed region corresponding to the first wiring portion.