The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2010
Filed:
Oct. 17, 2007
Minghao Shen, Sunnyvale, CA (US);
Shenqing Fang, Fremont, CA (US);
Wai Lo, Palo Alto, CA (US);
Christie R. K. Marrian, San Jose, CA (US);
Chungho Lee, Sunnyvale, CA (US);
Ning Cheng, San Jose, CA (US);
Fred Cheung, San Jose, CA (US);
Huaqiang Wu, Mountain View, CA (US);
Minghao Shen, Sunnyvale, CA (US);
Shenqing Fang, Fremont, CA (US);
Wai Lo, Palo Alto, CA (US);
Christie R. K. Marrian, San Jose, CA (US);
Chungho Lee, Sunnyvale, CA (US);
Ning Cheng, San Jose, CA (US);
Fred Cheung, San Jose, CA (US);
Huaqiang Wu, Mountain View, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.