The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 2010
Filed:
Dec. 15, 2008
Applicants:
Steve Fang, Sunnyvale, CA (US);
Chi Fung Cheng, San Jose, CA (US);
Inventors:
Steve Fang, Sunnyvale, CA (US);
Chi Fung Cheng, San Jose, CA (US);
Assignee:
Marvell International Ltd., Hamilton, BM;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/087 (2006.01);
U.S. Cl.
CPC ...
Abstract
A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.
Fang, Steve. (2010). Apparatus for low-jitter frequency and phase locked loop and associated methods (U.S. Patent No. 7825737). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7825737
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile