The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2010

Filed:

Mar. 14, 2007
Applicants:

Tsukasa Kobata, Sayama, JP;

Tsuyoshi Shiobara, Sayama, JP;

Kazuo Akaike, Sayama, JP;

Nobuo Tsukamoto, Akishima, JP;

Inventors:

Tsukasa Kobata, Sayama, JP;

Tsuyoshi Shiobara, Sayama, JP;

Kazuo Akaike, Sayama, JP;

Nobuo Tsukamoto, Akishima, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/085 (2006.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

An object of the present invention provides a frequency synthesizer having a broad frequency entraining range which can finely set a frequency over a broad band by a novel principle. As s specific solving means, a sinusoidal signal of an output frequency of a voltage-controlled oscillator is subjected to orthogonal detection, a vector rotating at the differential frequency (speed) between the output frequency and the frequency of the frequency signal used for the detection is created, and the frequency of a vector when the output frequency of the voltage-controlled oscillator is equal to a set value is calculated in advance. The voltage signal corresponding to the difference between the frequency of the vector and the calculated frequency is fed back to the voltage-controlled oscillator when the voltage-controlled oscillator is driven, and PLL is formed so that the difference is equal to zero. Accordingly, the output frequency of the voltage-controlled oscillator is adjusted to the set frequency when PLL is locked. After the difference between both the frequencies is increased after PLL is locked, the set value is integrated by the integrating circuit portion and added to the control voltage.


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