The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 2010
Filed:
Jun. 26, 2008
Xiaobao Wang, Cupertino, CA (US);
Chiakang Sung, Milpitas, CA (US);
Khai Q. Nguyen, San Jose, CA (US);
Sanjay K. Charagulla, San Jose, CA (US);
Xiaobao Wang, Cupertino, CA (US);
Chiakang Sung, Milpitas, CA (US);
Khai Q. Nguyen, San Jose, CA (US);
Sanjay K. Charagulla, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.