The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2010
Filed:
Apr. 16, 2008
Naoyuki Shigyo, Yokohama, JP;
Tetsuya Yamaguchi, Yokohama, JP;
Naoyuki Shigyo, Yokohama, JP;
Tetsuya Yamaguchi, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki-shi, JP;
Abstract
A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δ) for the wiring structure, a tolerance (ξ) for the capacitance variation ratio (ΔC/C), and a tolerance (ξ) for the resistance-by-capacitance variation ratio (Δ(RC)/(RC)), evaluates a fringe capacitance ratio (F=C/C) according to a fringe capacitance Cand parallel-plate capacitance Cof the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the following: The method employs an equivalent-variations condition defined as |ΔC/C|=|Δ(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure.