The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2010
Filed:
Jun. 09, 2007
Venkatesh Teeka Srinvasa Setty, Bangalore, IN;
Chandrashekar Lakshminarayanan, Thanjavur, IN;
Prasun Kali Bhattacharya, Burdwan, IN;
Prasenjit Bhowmik, Agartala, IN;
Chakravarthy Srinivasan, Bangalore, IN;
Mukesh Khatri, Indore, IN;
Sanjeeb Kumar Ghosh, Chandan-Pukur, IN;
Sumanth Chakkirala, Vasco-da-gama, IN;
Sundararajan Krishnan, Bangalore, IN;
Prakash Easwaran, Bangalore, IN;
Venkatesh Teeka Srinvasa Setty, Bangalore, IN;
Chandrashekar Lakshminarayanan, Thanjavur, IN;
Prasun Kali Bhattacharya, Burdwan, IN;
Prasenjit Bhowmik, Agartala, IN;
Chakravarthy Srinivasan, Bangalore, IN;
Mukesh Khatri, Indore, IN;
Sanjeeb Kumar Ghosh, Chandan-Pukur, IN;
Sumanth Chakkirala, Vasco-da-gama, IN;
Sundararajan Krishnan, Bangalore, IN;
Prakash Easwaran, Bangalore, IN;
Cosmic Circuits Private Limited, Bangalore, IN;
Abstract
A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.