The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2010

Filed:

Jun. 30, 2008
Applicants:

Ka Y. Leung, Austin, TX (US);

Donald E. Alfano, Round Rock, TX (US);

David P. Bresemann, Austin, TX (US);

Inventors:

Ka Y. Leung, Austin, TX (US);

Donald E. Alfano, Round Rock, TX (US);

David P. Bresemann, Austin, TX (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units. The capacitive isolation circuitry distributing a first portion of a high voltage isolation signal across a first group of capacitors associated with the first microcontroller unit and distributes a second portion of the high voltage isolation signal across a second group of capacitors associated with the second microcontroller unit. The capacitive isolation circuitry further transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream in accordance with the second clock frequency.


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