The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2010

Filed:

Dec. 28, 2007
Applicants:

Alberto Fazzi, Eindhoven, NL;

Luca Ciccarelli, Rimini, IT;

Luca Magagni, Bologna, IT;

Roberto Canegallo, Rimini, IT;

Roberto Guerrieri, Bologna, IT;

Inventors:

Alberto Fazzi, Eindhoven, NL;

Luca Ciccarelli, Rimini, IT;

Luca Magagni, Bologna, IT;

Roberto Canegallo, Rimini, IT;

Roberto Guerrieri, Bologna, IT;

Assignee:

STMicroelectronics, S.r.l., Agrate Brianza, IT;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
Abstract

An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage. The recovery stage comprises a first feedback loop connected to the first feedback node and acting in such a way to recover a received voltage signal and a feedback loop connected to the second feedback node of the state control stage and acting in such a way to deactivate the recovery feedback on the receiver node and guarantee that the receiver node is let in a high impedance state.


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