The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2010
Filed:
Sep. 27, 2007
Ralf Brederlow, Poing, DE;
Jessica Hartwich, Neubiberg, DE;
Christian Pacha, München, DE;
Wolfgang Rösner, Ottobrunn, DE;
Thomas Schulz, Austin, TX (US);
Ralf Brederlow, Poing, DE;
Jessica Hartwich, Neubiberg, DE;
Christian Pacha, München, DE;
Wolfgang Rösner, Ottobrunn, DE;
Thomas Schulz, Austin, TX (US);
Infineon Technologies, AG, Munich, DE;
Abstract
An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.