The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2010
Filed:
Feb. 15, 2007
Khurram Waheed, Acton, MA (US);
Jayawardan Janardhanan, Bangalore, IN;
Sameh S. Rezeq, Dallas, TX (US);
Robert B. Staszewski, Delft, NL;
Saket Jalan, Bangalore, IN;
Khurram Waheed, Acton, MA (US);
Jayawardan Janardhanan, Bangalore, IN;
Sameh S. Rezeq, Dallas, TX (US);
Robert B. Staszewski, Delft, NL;
Saket Jalan, Bangalore, IN;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.