The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2010

Filed:

Jul. 02, 2007
Applicants:

Sung-hwan Kim, Gyeonggi-do, KR;

Chang-woo OH, Gyeonggi-do, KR;

Yong-lack Choi, Seoul, KR;

Na-young Kim, Seoul, KR;

Inventors:

Sung-Hwan Kim, Gyeonggi-do, KR;

Chang-Woo Oh, Gyeonggi-do, KR;

Yong-Lack Choi, Seoul, KR;

Na-Young Kim, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a method of manufacturing a semiconductor device including a planar type transistor and a fin type transistor, a substrate having a first region and a second region is partially to form an isolation trench defining an isolation region and an active region. An insulation layer liner is formed on sidewalls of the isolation trench in the first region and the second region. An isolation layer fills an inner portion of the isolation trench. The insulation layer liner is partially removed to expose an upper surface of the substrate in the gate region of the first region, and an upper surface and sidewalls of the substrate in the gate region of the second region. A gate oxide layer and a gate electrode are formed on the exposed substrate.


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