The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2010
Filed:
Aug. 03, 2009
Tadashi Munakata, Nanae, JP;
Shingo Oosaka, Hakodate, JP;
Mitsuru Kinoshita, Hakodate, JP;
Yoshihiko Yamaguchi, Iide, JP;
Noriyuki Takahashi, Yonezawa, JP;
Tadashi Munakata, Nanae, JP;
Shingo Oosaka, Hakodate, JP;
Mitsuru Kinoshita, Hakodate, JP;
Yoshihiko Yamaguchi, Iide, JP;
Noriyuki Takahashi, Yonezawa, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Renesas Northern Japan Semiconductor, Inc., Chitose-shi, JP;
Abstract
A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.