Self programmable shared bist for testing multiple memories

Abstract

A built-in self-test (BIST) device tests multiple embedded memories of different characteristics. The BIST includes a BIST controller, a delay generator, multiple interface modules, and a memory wrapper. The BIST controller generates an initialization sequence and a memory test algorithm. The delay generator provides a delay of an expected data, a valid signal, a BBAD signal, a BEND signal, and a BFAIL signal. The multiple interface modules provide signal pipelining for multiple memories through a bus. The bus carries signals form the BIST device to multiple memories and vice-versa. The memory wrapper decodes a selected memory for decompressing a memory data signal generated by said BIST device and further compresses a memory output signal.