The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7814283 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 12, 2010

Filed:

Feb. 27, 2006
Applicants:

Devereaux C. Chen, Cupertino, CA (US);

Jeffrey R. Zimmer, Scotts Valley, CA (US);

Inventors:

Devereaux C. Chen, Cupertino, CA (US);

Jeffrey R. Zimmer, Scotts Valley, CA (US);

Assignee:

Juniper Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.


Find Patent Forward Citations

Chen, Devereaux. (2010). Low latency request dispatcher (U.S. Patent No. 7814283). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7814283

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