The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2010

Filed:

Oct. 13, 2009
Applicants:

Atsuo Hara, Fukuoka, JP;

Akihide Otonari, Fukuoka, JP;

Inventors:

Atsuo Hara, Fukuoka, JP;

Akihide Otonari, Fukuoka, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device for generating k-bit parallel pseudo-random data includes 'n' registers, from the first through the n-th registers ('n' is an integer not less than 3), and “k” exclusive-OR gates, from the first through the k-th exclusive-OR gates (“k” is an integer not less than 2). An output of the m-th register is input to the (m+k)th register (“m” is an integer between 1 and (n−k)). Outputs of the first through the (k−1)th exclusive-OR gates are respectively input to the second through the k-th exclusive-OR gates. An output of the first register is input to the first exclusive-OR gate. The outputs of the first through the k-th exclusive-OR gates are respectively input to the k-th through the first registers. Outputs of “k” registers, from the (n−k+1)th through the n-th registers are respectively input to the k-th through the first exclusive-OR gates, and also extracted as the k-bit parallel pseudo-random data.


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