The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2010

Filed:

Oct. 20, 2006
Applicants:

Andy L. Lee, San Jose, CA (US);

David Lewis, Toronto, CA;

Philip Pan, Fremont, CA (US);

James G. Schleicher, Ii, Los Gatos, CA (US);

Inventors:

Andy L. Lee, San Jose, CA (US);

David Lewis, Toronto, CA;

Philip Pan, Fremont, CA (US);

James G. Schleicher, II, Los Gatos, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable logic device having a Logic Element with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the N-stage LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT. In various embodiments, the non-LUT functions can include addition, subtraction, multiplication, division, digital signal processing, memory storage, etc.


Find Patent Forward Citations

Loading…