The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2010
Filed:
Nov. 05, 2007
Richard K. Williams, Cupertino, CA (US);
Donald Ray Disney, Cupertino, CA (US);
Jun-wei Chen, Saratoga, CA (US);
Wai Tien Chan, Hong Kong, CN;
Hyungsik Ryu, San Jose, CA (US);
Richard K. Williams, Cupertino, CA (US);
Donald Ray Disney, Cupertino, CA (US);
Jun-Wei Chen, Saratoga, CA (US);
Wai Tien Chan, Hong Kong, CN;
HyungSik Ryu, San Jose, CA (US);
Advanced Analogic Technologies, Inc., Santa Clara, CA (US);
Abstract
All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ 'as-implanted' dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.