The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2010
Filed:
Oct. 31, 2007
Do-hyun Kim, Seoul, KR;
Won-suk Shin, Yongin-si, KR;
Chang-oh Jeong, Suwon-si, KR;
Hong-sick Park, Suwon-si, KR;
Eun-guk Lee, Yongin-si, KR;
Je-hun Lee, Seoul, KR;
Do-Hyun Kim, Seoul, KR;
Won-Suk Shin, Yongin-si, KR;
Chang-Oh Jeong, Suwon-si, KR;
Hong-Sick Park, Suwon-si, KR;
Eun-Guk Lee, Yongin-si, KR;
Je-Hun Lee, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Abstract
A method for manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a silicon layer, and a conductor layer including a lower layer and an upper layer on the gate line, forming a photoresist film, on the conductor layer, patterning the photoresist film to form a photoresist pattern including a first portion and a second portion having a greater thickness than the first portion, etching the upper layer and the lower layer by using the photoresist pattern as art etch mask, etching the silicon layer by using the photoresist pattern as an etch mask to form a semiconductor, removing the second portion of the photoresist pattern by using an etch back process, selectively wet-etching the upper layer of the conductor layer by using the photoresist pattern as an etch mask, dry-etching the lower layer of the conductor layer by using the photoresist pattern as an etch mask to form a data line and a drain electrode including remaining upper and lower layers, and forming a pixel electrode connected to the drain electrode.