The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2010

Filed:

Sep. 30, 2005
Applicants:

Steven T. Mcclure, Northborough, MA (US);

Steven R. Chalmer, Newton, MA (US);

Brett D. Niver, Grafton, MA (US);

Inventors:

Steven T. McClure, Northborough, MA (US);

Steven R. Chalmer, Newton, MA (US);

Brett D. Niver, Grafton, MA (US);

Assignee:

EMC Corporation, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
Abstract

A process scheduling method includes executing a plurality of symmetric schedulers on respective processors of a multiprocessing system. Each scheduler periodically accesses a shared lock to obtain exclusive access to a shared scheduling data structure including (a) process information identifying the processes, and (b) scheduling information reflecting the executability and priorities of the processes. After obtaining the lock, each scheduler performs a scheduling routine including (a) utilizing the scheduling information and a scheduling algorithm to identify a next executable process, and (b) (1) activating the identified process to begin executing on the processor on which the scheduler is executing, and (2) updating the scheduling information to reflect the activation of the identified process. The scheduler then accesses the lock to relinquish exclusive access to the scheduling data structure. The fully symmetric scheduler provides for efficient, high-performance scheduling especially in embedded multiprocessing computer systems in which the rate of process context switches may be several thousand per second.


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