The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2010
Filed:
Nov. 15, 2004
Terry R. Jones, Livermore, CA (US);
Pythagoras C. Watson, Livermore, CA (US);
William Tuel, Kingston, NY (US);
Larry Brenner, Austin, TX (US);
Patrick Caffrey, Saugerties, NY (US);
Jeffrey Fier, Livermore, CA (US);
Terry R. Jones, Livermore, CA (US);
Pythagoras C. Watson, Livermore, CA (US);
William Tuel, Kingston, NY (US);
Larry Brenner, Austin, TX (US);
Patrick Caffrey, Saugerties, NY (US);
Jeffrey Fier, Livermore, CA (US);
Lawrence Livermore National Security, LLC, Livermore, CA (US);
Abstract
In a parallel computing environment comprising a network of SMP nodes each having at least one processor, a parallel-aware co-scheduling method and system for improving the performance and scalability of a dedicated parallel job having synchronizing collective operations. The method and system uses a global co-scheduler and an operating system kernel dispatcher adapted to coordinate interfering system and daemon activities on a node and across nodes to promote intra-node and inter-node overlap of said interfering system and daemon activities as well as intra-node and inter-node overlap of said synchronizing collective operations. In this manner, the impact of random short-lived interruptions, such as timer-decrement processing and periodic daemon activity, on synchronizing collective operations is minimized on large processor-count SPMD bulk-synchronous programming styles.