The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2010
Filed:
Sep. 11, 2007
James J. Curtin, Fishkill, NY (US);
William E. Dougherty, Jr., Pittsburgh, PA (US);
Jose L. Neves, Poughkeepsie, NY (US);
Douglas S. Search, Red Hook, NY (US);
James J. Curtin, Fishkill, NY (US);
William E. Dougherty, Jr., Pittsburgh, PA (US);
Jose L. Neves, Poughkeepsie, NY (US);
Douglas S. Search, Red Hook, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile