Arrangement, system and method for vector permutation in single-instruction multiple-data mircoprocessors

Abstract

A vector permutation system () for a single-instruction multiple-data microprocessor has a set of vector registers () which feed vectors to permutation logic () and then to a negate block () where they are permuted and selectively negated according to control parameters received from a selected one of a set of control registers (). A control arrangement () selects which control register is to provide the control parameters. In this way no separate permutation instructions are necessary or need to be executed, and no permutation parameters need to be stored in the vector registers (). This leads to higher performance, a smaller vector registers file and hence a smaller size of the microprocessor and better program code density.