The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2010

Filed:

Apr. 16, 2008
Applicants:

Paul Andrew Ashmore, Longmont, CO (US);

Dwight Oliver Lintz, Lyons, CO (US);

Gene Maine, Erie, CO (US);

Victor Key Pecone, Lyons, CO (US);

Rex Weldon Vedder, Boulder, CO (US);

Inventors:

Paul Andrew Ashmore, Longmont, CO (US);

Dwight Oliver Lintz, Lyons, CO (US);

Gene Maine, Erie, CO (US);

Victor Key Pecone, Lyons, CO (US);

Rex Weldon Vedder, Boulder, CO (US);

Assignee:

Dot Hill Systems Corporation, Longmont, CO (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.


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