The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2010
Filed:
Nov. 09, 2007
Applicant:
Hyuk-joon Kwon, Suwon-si, KR;
Inventor:
Hyuk-joon Kwon, Suwon-si, KR;
Assignee:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
Abstract
A power line layout for a semiconductor device includes a memory cell region, a plurality of wordline enable signal lines in the memory cell region, a plurality of first power lines arranged between the wordline enable signal lines in the memory cell region, and a plurality of second power lines arranged perpendicular to the first power lines in the memory cell region to form a mesh arrangement of first and second power lines.
Kwon, Hyuk-joon. (2010). Power line layout (U.S. Patent No. 7808804). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7808804
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile