The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2010
Filed:
Jun. 15, 2007
Shiro Sakiyama, Kyoto, JP;
Akinori Matsumoto, Osaka, JP;
Takashi Morie, Osaka, JP;
Shiro Dosho, Osaka, JP;
Yusuke Tokunaga, Hyogo, JP;
Shiro Sakiyama, Kyoto, JP;
Akinori Matsumoto, Osaka, JP;
Takashi Morie, Osaka, JP;
Shiro Dosho, Osaka, JP;
Yusuke Tokunaga, Hyogo, JP;
Panasonic Corporation, Osaka, JP;
Abstract
Each of n level shifters (LSto LS) includes an NMOS transistor (Mn) for receiving any one of n clock signals (Pto P) and a PMOS transistor (Mp) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp) included in each of the level shifters (LSto LS) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LSto LS) are equal to each other.