The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2010
Filed:
Jul. 28, 2008
Suk-pil Kim, Yongin-si, KR;
Yoon-dong Park, Yongin-si, KR;
Won-joo Kim, Suwon-si, KR;
Dong-gun Park, Seongnam-si, KR;
Eun-suk Cho, Suwon-si, KR;
Suk-kang Sung, Seongnam-si, KR;
Byung-yong Choi, Seongnam-si, KR;
Tae-yong Kim, Suwon-si, KR;
Choong-ho Lee, Seongnam-si, KR;
Suk-Pil Kim, Yongin-si, KR;
Yoon-Dong Park, Yongin-si, KR;
Won-Joo Kim, Suwon-si, KR;
Dong-Gun Park, Seongnam-si, KR;
Eun-Suk Cho, Suwon-si, KR;
Suk-Kang Sung, Seongnam-si, KR;
Byung-Yong Choi, Seongnam-si, KR;
Tae-Yong Kim, Suwon-si, KR;
Choong-Ho Lee, Seongnam-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.