The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2010

Filed:

Feb. 09, 2009
Applicants:

Teak-hoon Lee, Hwaseong-si, KR;

Pyoung-wan Kim, Suwon-si, KR;

Nam-seog Kim, Yongin-si, KR;

Chul-yong Jang, Yongin-si, KR;

Inventors:

Teak-Hoon Lee, Hwaseong-si, KR;

Pyoung-Wan Kim, Suwon-si, KR;

Nam-Seog Kim, Yongin-si, KR;

Chul-Yong Jang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/30 (2006.01); H01L 21/46 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs.


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