The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7805688 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 28, 2010

Filed:

Jan. 29, 2007
Applicants:

Noritoshi Yamakawa, Fukuoka, JP;

Hiroaki Miyamoto, Fukuoka, JP;

Yoshikatsu Kouhara, Fukuoka, JP;

Akitsugu Nakayama, Fukuoka, JP;

Kouichi Tanda, Fukuoka, JP;

Inventors:

Noritoshi Yamakawa, Fukuoka, JP;

Hiroaki Miyamoto, Fukuoka, JP;

Yoshikatsu Kouhara, Fukuoka, JP;

Akitsugu Nakayama, Fukuoka, JP;

Kouichi Tanda, Fukuoka, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical condition defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied. A circuit description-processing section executes circuit description by using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.


Find Patent Forward Citations

Yamakawa, Noritoshi. (2010). Memory construction apparatus for forming logical memory space (U.S. Patent No. 7805688). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7805688

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